The present invention relates to an on-die termination (ODT) device used in various kinds of semiconductor integrated circuits such as memory devices, and more particularly, to an ODT device with improved resolution.
Semiconductor devices are implemented into integrated circuit (IC) chips such as central processing units (CPUs), memories, and gate arrays, and are incorporated into a variety of electrical products such as personal computers, servers and workstations. Most of semiconductor devices include a receiving circuit configured to receive signals from an outside world via input pads and an output circuit configured to provide internal signals to an outside world via output pads.
As the operating speed of electrical products increases, a swing width of a signal exchanged between semiconductor devices gradually reduces to minimize a delay time taken for signal transmission. However, the reduction in the swing width of the signal has a great influence on an external noise, causing the signal reflectance to become more critical at an interface terminal due to an impedance mismatch. Such an impedance mismatch is generally caused by an external noise, a variation of a power voltage, a change of an operating temperature, a change of a manufacturing process, etc. The impedance mismatch may cause a difficulty in a high-speed transmission of data and a distortion in output data. Therefore, if semiconductor devices receive the distorted output signal through an input terminal, it frequently gives rise to problems such as a setup/hold failure and an error in a decision of an input level.
In particular, in order to resolve the above problems, a memory device requiring high-speed performance employs an impedance matching circuit, which is called an on-die termination (ODT), near around an input pad inside an IC chip. In a typical ODT scheme, source termination is performed by an output circuit at a transmitting end, and parallel termination is performed by a termination circuit connected in parallel with respect to a receiving circuit coupled to the input pad.
ZQ calibration refers to a procedure of generating pull-up and pull-down codes which are varied with PVT (process, voltage and temperature) conditions. The resistance of the ODT device, e.g., a termination resistance at a DQ pad in a memory device, is calibrated using the codes obtained from the ZQ calibration. Herein, the term of ZQ calibration is attributed to the fact that the calibration is performed using a ZQ node.
Hereinafter, how the ZQ calibration is performed in an ODT device will be more fully described.
FIG. 1 is a block diagram of a calibration circuit having only a pull-up resistor unit in a conventional ODT device.
The conventional calibration circuit having the pull-up resistor unit includes a comparator 102A, a counter 103A, a reference voltage generator 104A, and a pull-up resistor unit 110A configured with a plurality of parallel resistors which are turned on/off in response to pull-up calibration codes PCODE<0:N>.
The comparator 102A compares a voltage of a ZQ node and a reference voltage VREF (generally, ½VDDQ) generated from the reference voltage generator 104A with each other, thereby generating an up/down signal UP/DOWN. An external resistor 101A and the pull-up resistor unit 110A are connected to the ZQ node. Here, the external resistor 101A has a resistance of 240Ω generally, and particularly it is connected to a ZQ pad on the outside of the ZQ node chip. Therefore, the voltage of the ZQ node is determined through voltage division of the external resistor 101A and the pull-up resistor unit 110A.
The counter 103A receives the up/down signal UP/DOWN to generate the pull-up calibration codes PCODE<0:N>, and the pull-up resistor unit 110A calibrates its resistance according to the pull-up calibration codes PCODE<0:N>.
The calibrated resistance of the pull-up resistor unit 110A affects the ZQ node voltage again, and the above-described operation is then repeated until the ZQ node voltage is equal to the reference voltage VREF. Hence, the calibration is performed so that a total resistance of the pull-up resistor unit 110A is equal to that of the external resistor 101A, e.g., 240Ω in general.
The pull-up calibration codes PCODE<0:N> generated during the calibration are inputted to ODT resistors of an input buffer having the same configuration, and thus used for impedance matching.
However, in the case where the resistance of the external resistor 101A is 240Ω and a target resistance of the ODT resistor actually used in the input buffer is 60Ω (in this case, four ODT resistors which are equal to the calibration resistors are connected in parallel at the input buffer), there must be offsets between resistances of the resistors in the calibration circuit and the resistances of the resistors (i.e., ODT resistors) in the input buffer so that the ODT resistor has a resistance different from the target resistance, that is, the ODT resistor cannot have the resistance of 60Ω. Accordingly, the pull-up calibration codes PCODE<0:N> should be modified in order that the ODT resistor of the input buffer may have the target resistance.
FIG. 2 is a circuit diagram illustrating the conventional reference voltage generator 104A of FIG. 1.
The reference voltage VREF should be ½*VDDQ in general, but a switch option allows the reference voltage VREF to change from ½*VDDQ to other voltage levels, as shown in FIG. 2.
As described above, since the pull-up calibration codes PCODE<0:N> are generated by comparing the reference voltage VREF and the ZQ node voltage with each other, the pull-up calibration codes PCODE<0:N> can be different depending on the changing of the reference voltage VREF.
However, according to this conventional method, resistors included in the reference voltage generator are implemented with an active resistor, which leads to a problem in that a circuit area inevitably increases and further it is difficult to precisely calibrate an offset value, i.e., a difference from the target resistance.
FIG. 3 is a block diagram of a calibration circuit having pull-up and pull-down resistor units in a conventional ODT device.
The calibration circuit adapted to perform ZQ calibration operation includes a first pull-up resistor unit 110B, a second pull-up resistor unit 120, a pull-down drive resistor unit 130, a reference voltage generator 104B, first and second comparators 102B and 105, and pull-up and pull-down counters 103B and 106.
Because the first pull-up resistor unit 110B, the first comparator 102B, and the pull-up counter 103B are performed in the same manner as those of FIG. 1, further description for them will be omitted herein.
As illustrated in FIG. 1, the pull-up calibration codes PCODE<0:N> generated during the pull-up calibration operation are inputted to the second pull-up resistor unit 120, thus determining a total resistance of the second pull-up resistor unit 120. Then, pull-down calibration begins to perform in a manner similar to the pull-up calibration. Specifically, the pull-down calibration performs in such a manner that a voltage of a first node A is equal to the reference voltage VREF using the second comparator 105 and the pull-down counter 106, that is, the total resistance of the pull-down resistor unit 130 is equal to the total resistance of the second pull-up resistor unit 120.
The pull-up and pull-down calibration codes PCODE<0:N> and NCODE<0:N> resulted from the pull-up and pull-down calibration operations are inputted to pull-up and pull-down resistors provided at input/output pads, which are similarly configured as the pull-up and pull-down resistor units of the calibration circuit of FIG. 3, thus determining the resistance of the ODT device. In a memory device, resistances of pull-up and pull-down resistors at a DQ pad are determined.
FIGS. 4A and 4B are graphs illustrating resistance variations of a pull-up resistor unit at input/output pads versus the pull-up calibration codes PCODE<0:N> when a target resistance is set to 60Ω and 40Ω, respectively.
In FIGS. 4A and 4B, an X-axis denotes the pull-up calibration code PCODE<0:N> expressed as a decimal number equivalent to a binary pull-up calibration code, and a Y-axis denotes a resistance of a pull-up resistor unit at input/output pads in ohms.
Referring to FIGS. 4A and 4B, while the target resistances that the pull-up resistor units at the input/output pad must have are merely 60Ω and 40Ω, respectively, a width of resistance variation of the pull-up resistor unit is considerably great. The resistance of the pull-up resistor unit changes greatly as the pull-up calibration codes PCODE<0:N> change by each one level, as well.
As such, since the resistance of the pull-up resistor unit greatly changes with respect to the variation of the pull-up calibration codes PCODE<0:N>, it is difficult to accurately match the resistance of the pull-up resistor unit to the target resistance. Accordingly, there is a problem in achieving an accurate impedance matching of the ODT device, causing a speed of a semiconductor device employing the ODT device to be degraded.
Of course, it is possible to increase the resolution of the ODT device by increasing number of resistors connected to the pull-up resistor unit in parallel and more finely fractionating the pull-up calibration codes PCODE<0:N>. However, this leads to a drawback that a total circuit area must be increased, which is a trade-off relationship with high-resolution performance.